1. Field of the Invention
The present invention relates to an Ahuja compensation scheme, and in particular, an Ahuja compensated operational amplifier that eliminates the bias problem inherent in previous implementations.
2. Description of the Prior Art
The Ahuja frequency compensation scheme is a well-known frequency compensation for operational amplifiers. The Ahuja frequency compensation was developed to improve upon the well-known Miller compensation, which consists of coupling a capacitor across an output stage of an operational amplifier. The Ahuja frequency compensation implements an indirect coupling of this capacitor, by providing a third stage consisting of a compensating transistor coupled to the capacitor.
For a clearer representation of the Miller compensation and Ahuja compensation, please refer to FIG. 1. FIG. 1 is a diagram representing a Miller compensation scheme 100 and an Ahuja compensation scheme 200. As can be seen from the diagram, the Ahuja compensation scheme 200 implements a compensating transistor gm3 coupled to the capacitor CC and to a bias voltage VBIAS. The transistor itself is supplied with a bias current IBIAS. The benefits of the Ahuja compensation over the Miller compensation are a better ability to cope with high resistive and capacitive loading, reduced size of the capacitor CC, and better PSRR (power supply rejection ratio).
Please refer to FIG. 2. FIG. 2 shows the Ahuja compensation 200 in FIG. 1 implemented in a related art two stage operational amplifier 300. The operational amplifier 300 comprises an input stage coupled to a differential current source, the input stage comprising transistors MP5, MP1a, MP1b, MN1a and MN1b. The input stage is coupled to an output stage comprising transistors MP2 and MN2, and coupled between a supply voltage VDD and ground. The compensating transistor MP3 is coupled to bias voltage VBP2 and compensating capacitor CC. MP3 is further coupled to MP4 which is coupled between VDD and bias voltage VBP1 for supplying MP3 with the bias current IBIAS. The circuit further comprises transistors MN3 and MN4, which are coupled to MP3, MN2, MN1b, and respectively coupled to bias voltages VBN1 and VBN2. The purpose of MN3 and MN4 is to provide a path for the current IBIAS in MP3 and MP4 to ground.
The disadvantage of this circuit is that MN3 and MN4 must be biased using VBN1 and VBN2 to carry exactly the current IBIAS in MP3 and MP4 biased separately using VBP2 and VBP1. Since it is not practically possible to bias a p-channel transistor and an n-channel transistor separately to carry exactly the same current, this objective is never met. The consequence of this is that the DC offset voltage of the operational amplifier is high.
Furthermore, the Ahuja compensation scheme 200 illustrated in FIG. 1 does not achieve the desired benefits under certain conditions such as light capacitive loading. Therefore, both the original Ahuja compensation 200 and the Ahuja compensated operational amplifier 300 need to be improved.